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| M27V320 32 Mbit (4Mb x8 or 2Mb x16) OTP EPROM s 3.3V 10% SUPPLY VOLTAGE in READ OPERATION ACCESS TIME: 100ns BYTE-WIDE or WORD-WIDE CONFIGURABLE 32 Mbit MASK ROM REPLACEMENT LOW POWER CONSUMPTION - Active Current 30mA at 5MHz - Standby Current 60A SO44 (M) TSOP48 (N) 12 x 20 mm s s s s s s s PROGRAMMING VOLTAGE: 12V 0.25V PROGRAMMING TIME: 50s/word ELECTRONIC SIGNATURE: - Manufacturer Code 20h - Device Code: 32h Figure 1. Logic Diagram DESCRIPTION The M27V320 is a low voltage 32 Mbit EPROM offered in the OTP range (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage. It is organised as either 4 MWords of 8 bit or 2 MWords of 16 bit. The pin-out is compatible with the 32 Mbit Mask ROM. The M27V320 is offered in SO44 and TSOP48 (12 x 20 mm) packages. VCC 21 A0-A20 15 Q15A-1 Q0-Q14 E GVPP M27V320 BYTE VSS AI05852 August 2002 1/15 M27V320 Figure 2. SO Connections Figure 3. TSOP Connections NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS GVPP Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 44 1 43 2 3 42 4 41 40 5 39 6 38 7 37 8 36 9 35 10 34 11 M27V320 33 12 32 13 31 14 30 15 29 16 17 28 18 27 19 26 20 25 21 24 22 23 AI05853 A20 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC BYTE A16 A15 A14 A13 A12 A11 A10 A9 A8 A19 VSS A20 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E 1 48 12 13 M27V320 37 36 24 25 AI05854 VSS VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC VCC VSS Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 GVPP VSS VSS Table 1. Signal Names A0-A20 Q0-Q7 Q8-Q14 Q15A-1 E GVPP BYTE VCC VSS NC Address Inputs Data Outputs Data Outputs Data Output / Address Input Chip Enable Output Enable / Program Supply Byte-Wide Select Supply Voltage Ground Not Connected Internally DEVICE OPERATION The operating modes of the M27V320 are listed in the Operating Modes Table. A single power supply is required in the read mode. All inputs are TTL compatible except for VPP and 12V on A9 for the Electronic Signature. Read Mode The M27V320 has two organisations, Word-wide and Byte-wide. The organisation is selected by the signal level on the BYTE pin. When BYTE is at VIH the Word-wide organisation is selected and the Q15A-1 pin is used for Q15 Data Output. When the BYTE pin is at VIL the Byte-wide organisation is selected and the Q15A-1 pin is used for the Address Input A-1. When the memory is logically regarded as 16 bit wide, but read in the Byte-wide organisation, then with A-1 at VIL the lower 8 bits of the 16 bit data are selected and with A-1 at VIH the upper 8 bits of the 16 bit data are selected. 2/15 M27V320 Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) VCC VA9 (2) VPP Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage (except A9) Supply Voltage A9 Voltage Program Supply Voltage Value -40 to 125 -50 to 125 -65 to 150 -2 to 7 -2 to 7 -2 to 13.5 -2 to 14 Unit C C C V V V V Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is -0.5V with possible undershoot to -2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes Mode Read Word-wide Read Byte-wide Upper Read Byte-wide Lower Output Disable Program Program Inhibit Standby Electronic Signature E VIL VIL VIL VIL VIL Pulse VIH VIH VIL GVPP VIL VIL VIL VIH VPP VPP X VIL BYTE VIH VIL VIL X VIH VIH X VIH A9 X X X X X X X VID Q15A-1 Data Out VIH VIL Hi-Z Data In Hi-Z Hi-Z Code Q14-Q8 Data Out Hi-Z Hi-Z Hi-Z Data In Hi-Z Hi-Z Codes Q7-Q0 Data Out Data Out Data Out Hi-Z Data In Hi-Z Hi-Z Codes Note: X = VIH or VIL, VID = 12V 0.5V. Table 4. Electronic Signature Identifier Manufacturer's Code Device Code A0 VIL VIH Q7 0 0 Q6 0 0 Q5 1 1 Q4 0 1 Q3 0 0 Q2 0 0 Q1 0 1 Q0 0 0 Hex Data 20h 32h Note: Outputs Q15-Q8 are set to '0'. 3/15 M27V320 Table 5. AC Measurement Conditions High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V Standard 20ns 0.4V to 2.4V 0.8V and 2V Figure 4. AC Testing Input Output Waveform Figure 5. AC Testing Load Circuit 1.3V High Speed 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V AI01822 1N914 3.3k Standard 2.4V OUT CL 0.4V CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance AI01823B Table 6. Capacitance (1) (TA = 25 C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 10 12 Unit pF pF Note: 1. Sampled only, not 100% tested. The M27V320 has two control functions, both of which must be logically active in order to obtain data at the outputs. In addition the Word-wide or Byte-wide organisation must be selected. Chip Enable (E) is the power control and should be used for device selection. Output Enable (GVPP) is the output control and should be used to gate data to the output pins independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of GVPP, assuming that E has been low and the addresses have been stable for at least tAVQVtGLQV. Standby Mode The M27V320 has standby mode which reduces the supply current from 50mA to 100A. The M27V320 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPP input. 4/15 M27V320 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70C or -40 to 85C; VCC = 3.3V 10%; VPP = VCC) Symbol ILI ILO ICC ICC1 ICC2 IPP VIL VIH (2) VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL IOL = 2.1mA IOH = -400A 2.4 Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, GVPP = VIL, IOUT = 0mA, f = 5MHz, VCC 3.6V E = VIH E > VCC - 0.2V, VCC 3.6V VPP = VCC -0.6 0.7VCC Min Max 1 10 30 1 60 10 0.2VCC VCC + 0.5 0.4 Unit A A mA mA A A V V V V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V. Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while GVPP should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the supplies to the devices. The supply current ICC has three segments of importance to the system designer: the standby current, the active current and the transient peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device outputs. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1F ceramic capacitor is used on every device between VCC and VSS. This should be a high frequency type of low inherent inductance and should be placed as close as possible to the device. In addition, a 4.7F electrolytic capacitor should be used between VCC and VSS for every eight devices. This capacitor should be mounted near the power supply connection point. The purpose of this capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. 5/15 M27V320 Table 8. Read Mode AC Characteristics (1) (TA = 0 to 70C or -40 to 85C; VCC = 3.3V 10%) M27V320 Symbol Alt Parameter Test Condition -100 (3) Min tAVQV tBHQV tELQV tGLQV tBLQZ (2) tEHQZ (2) tGHQZ (2) tAXQX tBLQX tACC tST tCE tOE tSTD tDF tDF tOH tOH Address Valid to Output Valid BYTE High to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid BYTE Low to Output Hi-Z Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition BYTE Low to Output Transition E = VIL, GVPP = VIL E = VIL, GVPP = VIL GVPP = VIL E = VIL E = VIL, GVPP = VIL GVPP = VIL E = VIL E = VIL, GVPP = VIL E = VIL, GVPP = VIL 0 0 5 5 Max 100 100 100 45 45 45 45 0 0 5 5 -120 Min Max 120 120 120 50 50 50 50 0 0 5 5 -150 Min Max 150 150 150 60 50 50 50 ns ns ns ns ns ns ns ns ns Unit Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. Speed obtained with High Speed AC measurement conditions. Figure 6. Word-Wide Read Mode AC Waveforms A0-A20 VALID tAVQV tAXQX VALID E tGLQV GVPP tELQV Q0-Q15 tGHQZ Hi-Z tEHQZ AI02207 Note: BYTE = VIH. 6/15 M27V320 Figure 7. Byte-Wide Read Mode AC Waveforms A0-A20 VALID tAVQV tAXQX VALID E tGLQV GVPP tELQV Q0-Q7 tGHQZ Hi-Z tEHQZ AI02218 Note: BYTE = VIL. Figure 8. BYTE Transition AC Waveforms A0-A20 VALID A-1 tAVQV BYTE VALID tAXQX tBHQV Q0-Q7 tBLQX Hi-Z Q8-Q15 tBLQZ AI02219 DATA OUT DATA OUT Note: E = VIL; GVPP = VIL . 7/15 M27V320 Table 9. Programming Mode DC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12V 0.25V) Symbol ILI ICC IPP VIL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = -2.5mA 3.5 11.5 12.5 E = VIL -0.3 2.4 Test Condition VIL VIN VIH Min Max 10 50 50 0.8 VCC + 0.5 0.4 Unit A mA mA V V V V V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Table 10. MARGIN MODE AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12V 0.25V) Symbol tA9HVPH tVPHEL tA10HEH tA10LEH tEXA10X tEXVPX tVPXA9X Alt tAS9 tVPS tAS10 tAS10 tAH10 tVPH tAH9 Parameter VA9 High to VPP High VPP High to Chip Enable Low VA10 High to Chip Enable High (Set) VA10 Low to Chip Enable High (Reset) Chip Enable Transition to VA10 Transition Chip Enable Transition to VPP Transition VPP Transition to VA9 Transition Test Condition Min 2 2 1 1 1 2 2 Max Unit s s s s s s s Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Programming When delivered, all bits of the M27V320 are in the '1' state. Data is introduced by selectively programming '0's into the desired bit locations. Although only '0's will be programmed, both '1's and '0's can be present in the data word. The M27V320 is in the programming mode when VPP input is at 12.5V, GVPP is at VIH and E is pulsed to VIL. The data to be programmed is applied to 16 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V 0.25V. 8/15 M27V320 Table 11. Programming Mode AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12V 0.25V) Symbol tAVEL tQVEL tVCHEL tVPHEL tVPLVPH tELEH tEHQX tEHVPX tVPLEL tELQV tEHQZ (2) tEHAX Alt tAS tDS tVCS tOES tPRT tPW tDH tOEH tVR tDV tDFP tAH Parameter Address Valid to Chip Enable Low Input Valid to Chip Enable Low VCC High to Chip Enable Low VPP High to Chip Enable Low VPP Rise Time Chip Enable Program Pulse Width (Initial) Chip Enable High to Input Transition Chip Enable High to VPP Transition VPP Low to Chip Enable Low Chip Enable Low to Output Valid Chip Enable High to Output Hi-Z Chip Enable High to Address Transition 0 0 Test Condition Min 1 1 2 1 50 45 2 2 1 1 130 55 Max Unit s s s s ns s s s s s ns ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. Figure 9. MARGIN MODE AC Waveforms VCC A8 A9 tA9HVPH GVPP tVPHEL E tA10HEH A10 Set tEXA10X tEXVPX tVPXA9X A10 Reset tA10LEH AI00736B Note: A8 High level = 5V; A9 High level = 12V. 9/15 M27V320 Figure 10. Programming and Verify Modes AC Waveforms A0-A20 tAVEL Q0-Q15 tQVEL VCC tVCHEL GVPP tVPHEL E DATA IN VALID tEHAX DATA OUT tEHQX tEHQZ tEHVPX tELQV tVPLEL tELEH PROGRAM VERIFY AI02205 Note: BYTE = VIH; GVPP High level = 12V. Figure 11. Programming Flowchart VCC = 6.25V, VPP = 12V SET MARGIN MODE n=0 E = 50s Pulse NO ++n = 25 YES NO VERIFY YES Last Addr NO ++ Addr FAIL YES RESET MARGIN MODE CHECK ALL WORDS BYTE = VIH 1st: VCC = 5V 2nd: VCC = 3V AI05820 PRESTO III Programming Algorithm The PRESTO III Programming Algorithm allows the whole array to be programed with a guaranteed margin in a typical time of 100 seconds. Programming with PRESTO III consists of applying a sequence of 50s program pulses to each word until a correct verify occurs (see Figure 11). During programing and verify operation a MARGIN MODE circuit must be activated to guarantee that each cell is programed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides the necessary margin to each programmed cell. Program Inhibit Programming of multiple M27V320s in parallel with different data is also easily accomplished. Except for E, all like inputs including GVPP of the parallel M27V320 may be common. A TTL low level pulse applied to a M27V320's E input and VPP at 12V, will program that M27V320. A high level E input inhibits the other M27V320s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with GVPP at VIL. Data should be verified with tELQV after the falling edge of E. 10/15 M27V320 Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25C 5C ambient temperature range that is required when programming the M27V320. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27V320, with VPP = VCC = 5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics M27V320, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0. 11/15 M27V320 Table 12. Ordering Information Scheme Example: Device Type M27 Supply Voltage V = 3.3V 10% Device Function 320 = 32 Mbit (4Mb x 8 or 2Mb x 16) Speed -100(1) = 100 ns -120 = 120 ns -150 = 150 ns Package M = SO44 N = TSOP48: 12 x 20 mm Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C M27V320 -100 M 1 Note: 1. High Speed, see AC Characteristics section for further information. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Table 13. Revision History Date December 2001 26-Aug-2002 Version 1.0 1.1 First Issue Document status moved to Data Sheet Revision Details 12/15 M27V320 Table 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data millimeters Symbol Typ A A1 A2 b C CP D e E EH L N 44 28.20 1.27 13.30 16.00 0.80 8 44 28.00 - 13.20 15.75 2.30 0.40 0.15 0.10 2.20 0.35 0.10 2.40 0.50 0.20 0.08 28.40 - 13.50 16.25 1.1102 0.0500 0.5236 0.6299 0.0315 8 1.1024 - 0.5197 0.6201 0.0906 0.0157 0.0059 Min Max 2.80 0.0039 0.0866 0.0138 0.0039 0.0945 0.0197 0.0079 0.0030 1.1181 - 0.5315 0.6398 Typ Min Max 0.1102 inches Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline A2 b e D A C CP N E EH 1 A1 L SO-d Drawing is not to scale. 13/15 M27V320 Table 15. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data mm Symb Typ A A1 A2 B C CP D D1 E e L N 0.50 19.80 18.30 11.90 0.50 0 48 0.05 0.95 0.17 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 0.10 20.20 18.50 12.10 0.70 5 0.020 0.780 0.720 0.469 0.020 0 48 0.002 0.037 0.007 0.004 Typ Min Max 0.047 0.006 0.041 0.011 0.008 0.004 0.795 0.728 0.476 0.028 5 inches Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline A2 1 N e E B N/2 D1 D A CP DIE C TSOP-a A1 L Drawing is not to scale. 14/15 M27V320 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Austalia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com (c) 15/15 |
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